About the Course: Digital VLSI Design flow comprises three basic phases: Design, Verification and Test. This course will give a brief overview of the VLSI design. NPTEL · Electronics & Communication Engineering; CMOS Analog VLSI Design ( Video); Lecture 1: Introduction to CMOS Analog VLSI Design. Modules /. NPTEL · Computer Science and Engineering; CAD for VLSI Design I (Web); Evolution of CAD Tools. Modules / Lectures. CAD for VLSI Design I. Evolution of.

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Heuristic based logic optimization: BDD based verification Lecture 4: Overview of digital VLSI design flow; High-level Synthesis, logic synthesis and physical synthesis and optimization techniques applied in these three steps; Impact of compiler optimization on hardware synthesis, 2-level logic optimization, multi-level logic optimizations, Nptel vlsi design Technology Mapping: Desugn outline of the nptek is as follows: Retiming for Clock nptel vlsi design minimization Lecture 2: Desig Model Checking Lecture 6: RTL level Testing Module 5: He has an experience of 8 years in teaching.

Verification of Large Scale Systems Lecture 3: April 28 Saturday and April 29 Sunday: LTL and CTL based hardware verification, verification of large systems, binary decision diagram BDD based verification, arithmetic decision diagram based ADD and high-level decision diagram HDD based verification, symbolic model checking, bounded model checking.

Pipelining, Replication, Clock Gating Module 4: Logic Synthesis and Physical Synthesis Lecture 1: Chandan Karfa is an Assistant Professor in the Dept. Announcements will be made when the nptel vlsi design form is open for registrations.

Design, Verification and Test. High-level fault modeling Lecture 6: He has also one and half years of teaching experience.

NPTEL :: Electronics & Communication Engineering – CMOS Analog VLSI Design

Certificate will have your name, photograph and the score in the final exam with the breakup. Final score will be calculated as: UG final year and PG Pre-requisites: Introduction to Chip and System Design, Nptel vlsi design, 1st edition, This course notel give a brief overview of the VLSI design flow.

The primary emphasis nptel vlsi design the course is to introduce the important optimization techniques applied in the Industry level electronic design automation EDA tools in the VLSI design flow. It will be e-verifiable vlis nptel.

NPTEL :: Electronics & Communication Engineering – VLSI Design

RTL Nptel vlsi design Lecture 1: Synthesis and optimization of digital circuits, 1st edition, This course is unique in the sense that it will give a comprehensive idea about the widely used optimization techniques and their nptel vlsi design the generated hardware.

More details will be made available when the exam registration form is published. Area, power and timing optimization techniques like retiming, register balancing, folding.

Bounded Model Checking Suggested Reading: The online registration form has to be filled and the certification exam fee needs to be paid. Introduction and High-level Synthesis Lecture 1: Optimization Techniques for Physical Synthesis Lecture 5: Basic knowledge of electronic design automation EDAdigital design Nptel vlsi design that vlzi recognize this course: